A FPGA based Steganographic System Implementing a Modern Steganalysis Resistant LSB Algorithm

Steganography differs from other data hiding techniques because it encodes secret message inside cover object in such a way that transmission of secret message also remains a secret. Widespread usage of digital images, lower computational complexity and better performance makes spatial domain steganographic algorithms well suited for hardware implementation, which are not very frequent. This work tries to implement a modern steganalysis resistant LSB algorithm on FPGA based hardware. The presented work also optimises various operations and elements from original one third probability algorithm with respect to hardware implementation. The target FPGA for the implementation is Xilinx SP605 board (Spartan 6 series XC6SLX45T FPGA). Stego images obtained by the implementation have been thoroughly examined for various qualitative and quantitative aspects, which are found to be at par with original algorithm.

Elliptic Curve Scalar Multiplier Design Using FPGAs

A compact fast elliptic curve scalar multiplier with variable key size is implemented as a coprocessor with a Xilinx FPGA. This implementation utilizes the internal SRAM/registers of the FPGA and has the whole scalar multiplier implemented within a single FPGA chip. The compact design helps reduce the overhead and limitations associated with data transfer between FPGA and host, and thus leads to high performance. The experimental data from the mappings over small fields shows that the carefully constructed hardware architecture is regular and has high CLB utilization.